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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2005, zarlink semiconductor inc. all rights reserved. features ? dvb-c en300429 and itu-t j.83 annex a/c compliant qam demodulator ? conventional if and low if input supported ? qam constellations 16, 32, 64, 128 and 256 ? symbol rates up to 9 mbaud ? blind acquisition of all symbol rates ? blind acquisition of qam constellations ? single if filter bandwidth for all symbol rates ? signal level, ber and snr indicators ? programmable if/rf agc take-over point ? power down mode under software control ? parallel and serial mpeg outputs ? external 4 or 27 mhz clock or single low-cost 10 mhz crystal ? small package size lqfp64 7x7 mm ? power consumption <300 mw at 6.9 mbaud ? 5 v tolerant 2-wire bus control interface ? 5 v tolerant gpio port and agc outputs ? rf level detect facility via a separate adc ? very low driver software overhead due to on-chip state-machine control. ? general purpose programmable timer applications ? set-top boxes ? digital cable ready tv applications ? cable modems ?smatv/matv receivers description the zl10210 is a dvb-c and itu-t annex a/c qam demodulator. this low power cable demodulator includes standard zarlink feat ures of auto signal acqui- sition, fast blind-scan cap ability, software/hardware power down, rf level, ber and snr detection. the zl10210 represents the latest in qam demodulation for dvb cable. together with a cable tuner, a full digital cable receiver front-end can be realized. either conventional intermediate frequencies such as 36 or 44 mhz or low intermediate frequencies can be used - see application below. the zl10210 requires only a single channel filter bandwidth of 8 mhz nominal for full dvb and itu-t annex a/c performance. the low power consumption, small package form factor and integrated software/hardware power-down modes help reduce the system bom (bill of materials) in cost sensitive applications. the device is packaged in a 7 x 7 mm 64-pin lqfp. functional description the zl10210 accepts an analog signal from the tuner, either at low intermediate frequency (if) or conven- tional if up to 50 mhz, and delivers an mpeg2 compliant transport stream. it contains a single 10-bit november 2005 ordering information zl10210/gc/gp1n 64 pin lqfp -40 o c to +85 o c zl10210 dvb-c cable channel demodulator data sheet figure 1 - system diagram
zl10210 data sheet 2 zarlink semiconductor inc. analog-to-digital converter (adc), a digital qam demodu lator and forward error correcting (fec) decoder. the qam demodulator supports qam constellations 16 to 256. both the qam demodulator and the fec are dvb and itu-t j.83 annex a/c compliant. figure 2 - zl10210 functional diagram the adc uses a fixed sample rate greater than four times the maximum symbol rate. hence for 1 to 9 mbaud appli- cations, the signal has to be sampled at a frequency ar ound 36 mhz. the spectrum of the analog signal being sampled may be located at near-zero if (e.g. centered at 9 mhz) or it may be located at a conventional if such as 36.2 mhz or 43.5 mhz. first consider the case of if sampling a 1 to 7 mbaud qam signal centered at 36.2 mhz intermediate frequency. the sampling frequency chosen for this application is 28.9 m hz. this sampling process will fold the 36.2 mhz if spectrum to one centered at 7.3 mhz. second consider the case of if sampling a 1 to 6 mb aud qam signal centered at 43.5 mhz if. the sampling frequency chosen for this application is 25 mhz. this samp ling process will result in a qam spectrum centered at 6.5 mhz. in the second case the sampling process results in spectral inversion. even in first case the if spectrum may be spectrally inverted. however, spectral inversion is not an issue with zl10210 since it automatically detects and corrects for this in the digital domain. the digital signal is first mixed down to baseband. however, as a result of tuning errors this signal will not be centered at zero frequency. zl10210 has an automatic frequency control (afc) loop that can track out tuning errors and hence in the tracking phase th is signal will be cent ered at zero frequency. the afc loop can typically compensate for +/-350 khz frequency offs ets. larger offsets can be correct ed by programming on- chip registers. the baseband signal is filtered to reduce the effect of ad jacent channels. additional on-chip digital filtering is provided for low symbol rate applications. for exampl e, it is possible to demodulate and decode a 1 mbaud qam signal using only one external 8 mhz saw filter.
zl10210 data sheet 3 zarlink semiconductor inc. zl10210 has co mplete blind acquisition capability. it can automatically search and lock on to any qam constel- lation in the set 16, 32, 64, 128 and 256. it can compensate for spectral inversion. it can also automatically acquire a symbol rate in the range 1 to 7 mbaud correcting for any tuning errors and adapting the filter bandwidths to signal bandwidth. all these functions are implemented using a soph isticated built-in control state machine with no software intervention. the symbol-spaced equalizer in the zl10210 is designed to acquire the qam signal in blind mode, i.e., with no training sequence, and then to track the signal in the decision feedback mode. the equalizer has a feed-forward segment and a feedback segments. the tap partitioning bet ween feed-forward and feedback is fully programmable. the symbol timing and phase recovery functions with the zl10210 are fully digital. the timing recovery phase locked loop has a built in timing sweep to enable the zl10210 to lock on to unknown symbol rates. the phase recovery loop has been optimised to overcome ph ase noise degradation caused by typical tuners. the zl10210 qam demodulator has built in control mechanisms to overcome signal degradation due to impulse noise in cable systems. the most significant bits of the demodulated i/q symbols are differentially decoded to remove multiples of 90 degree phase ambiguity in demodul ation. the qam symbols are then demapped into a bit stream, using the constellation definitions provided by dvb and itu-t. the number of bits per symbol is eight for qam-256, seven for qam-128, six for qam-64 , five for qam-32 and four for qam-16. the bitstream is aligned into bytes and then into 204-byte frames by the frame alignm ent unit. these frames are deinterleaved as defined by dvb to improve the resili ence of the system to error bursts. the (204,188) reed- solomon decoder, which follows the deinterleaver, can co rrect up to eight byte-errors per frame. this also generates an uncorrectable er ror flag for blocks with more than eight byte-errors. in additi on, the zl10210 reed- solomon decoder keeps a count of the number of uncorrect able blocks and the number of bit errors corrected. the former will give an indication on the quality of the mpeg output and the latte r provides the bit error rate in qam demodulation. the decoder packets are then descrambled to reverse the e nergy dispersal function introduced by the transmitter. the output of the device is a stream of regularly spaced mpeg packets. the mpeg byte clock frequency is automatically adapted to be the minimum needed for a given sy mbol rate and qam constellation. alternatively the mpeg bytes can be clocked out using an externally prov ided byte clock. there is also an option for bit-serial output.
zl10210 data sheet 4 zarlink semiconductor inc. figure 3 - typical zl10210 application
zl10210 data sheet 5 zarlink semiconductor inc. 1.0 pin & package details 1.1 pin outline figure 4 below shows the pi n functions of the zl10210. figure 4 - pin outline 1.2 pin allocation pin function pin function pin function pin function 1 vdd 17 gpp0 33 vdd 49 mdo0 2 cvdd 18 sadd4 34 rflev 50 mdo1 3 gnd 19 reset 35 gnd 51 mdo2 4 sadd3 20 sleep 36 cvdd 52 mdo3 5 sadd2 21 plltest 37 sadd1 53 mdo4 6irq 22 pllvdd 38 sadd0 54 mdo5 7 cvdd 23 gnd 39 agc2/gpp1 55 vdd 8 gnd 24 xti 40 agc1 56 gnd table 1 - pin names - numeric
zl10210 data sheet 6 zarlink semiconductor inc. 9 clk1 25xto 41gnd 57cvdd 10 data1 26 gnd 42 cvdd 58 gnd 11 cvdd 27 oscmode 43 vdd 59 mdo6 12 gnd 28 avdd 44 gnd 60 mdo7 13 smtest 29 gnd 45 clk2 61 moclk 14 status 30 vin 46 data2 62 bkerr 15 gnd 31 vin 47 mostrt 63 miclk 16 vdd 32 gnd 48 moval 64 gnd function pin function pin function pin function pin agc1 40 gnd 12 mdo2 51 sadd1 37 agc2/gpp1 39 gnd 15 mdo3 52 sadd2 5 avdd 28 gnd 23 mdo4 53 sadd3 4 bkerr 62 gnd 26 mdo5 54 sadd4 18 clk1 9 gnd 29 mdo6 59 sleep 20 clk2 45 gnd 32 mdo7 60 smtest 13 cvdd 2 gnd 35 miclk 63 status 14 cvdd 7 gnd 41 moclk 61 vdd 1 cvdd 11 gnd 44 mostrt 47 vdd 16 cvdd 36 gnd 56 moval 48 vdd 33 cvdd 42 gnd 58 oscmode 27 vdd 43 cvdd 57 gnd 64 plltest 21 vdd 55 data1 10 gpp0 17 pllvdd 22 vin 30 data2 46 irq 6 reset 19 vin 31 gnd 3 mdo0 49 rflev 34 xti 24 gnd 8 mdo1 50 sadd0 38 xto 25 table 2 - pin names - alphabetical order pin function pin function pin function pin function table 1 - pin names - numeric (continued)
zl10210 data sheet 7 zarlink semiconductor inc. 1.3 pin description pin description table pin no name pin description i/ o type v 1 ma mpeg pins 47 mostrt mpeg packet start o cmos tristate 3.3 1 48 moval mpeg data valid o 3.3 1 49-54, 59-60 mdo(0:5) mdo(6:7) mpeg data outputs o 3.3 1 61 moclk mpeg output clock o 3.3 1 62 bkerr block error output o 3.3 1 63 miclk mpeg input clock i cmos 3.3 14 status status output o 3.3 1 6irq interrupt output o open drain 56 control pins 9 clk1 serial clock i cmos 5 10 data1 serial data i/ o open drain 56 24 xti low phase noise crystal oscillator icmos 1.8 25 xto i/ o 1.8 20 sleep device power down i 5 4, 5,18,37,38 sadd(4:0) serial address set i 3.3 13 smtest production test (only set low) i 3.3 45 clk2 serial clock tuner i/ o open drain 56 46 data2 serial data tuner i/ o 56 40 agc1 primary agc o 56 39 agc2/gpp1 secondary agc or general i/o i/ o 56 17 gpp0 general purpose i/o i/ o 56 19 reset device reset - active low i cmos 5
zl10210 data sheet 8 zarlink semiconductor inc. 27 oscmode crystal oscillator mode: low = crystal oscillator high = external clock icmos 3.3 21 plltest pll test - do not connect o (tristated) analog inputs 30 vin adc positive input i analog input nominally 400 mv ac coupled 31 vin adc negative input i 34 rflev rf level adc input i analog input nominally 3.3 v for max. level 3.3 supply pins 28 avdd adc analog supply 2 s 1.8 2, 7, 11, 36, 42, 57 cvdd core logic power s 22 pllvdd pll supply 2 s 1, 16, 33, 43, 55 vdd i/o ring power (#33 is to adc only 2 ) s 3.3 3, 8, 12, 15, 23, 26, 29, 32, 35, 41, 44, 56, 58, 64 gnd core, analog and i/o grounds 3 s 0 1. this column is the nominal maximum for a given pin. pins list ed as 5 v can tolerate voltages up to 5 v (inputs have threshold voltages related to the 3v3 supply). 2. pins #22, #28 and #33 should have separate supply lines from the digital supplies of the same voltage. 3. decoupling capacitors should be used from every gnd pin to its adjacent supply pin, with the capacitor as close as possible to the pins. pin #26 is provided to allow the oscillator to be ringed. pin description table (continued) pin no name pin description i/ o type v 1 ma
zl10210 data sheet 9 zarlink semiconductor inc. 2.0 interfaces 2.1 2-wire bus 2.1.1 host the primary 2-wire bus serial interface uses pins: ? data1 (pin #10) serial data, the most significant bit is sent first. ? clk1 (pin #9) serial clock. the 2-wire bus address is determined by app lying vdd or gnd to the sadd[4:0] pins. in cnim evaluation applications, the 2- wire bus address is 0001 111 r/w with the pins connected as follows: when the zl10210 is powered up, the reset pin 9 should be held low for at least 50 ms after vdd has reached normal operation levels. as the reset pin goes high, the logic levels on sad d[4:0] are latched as the 2-wire bus address. addr[0] is the r/w bit. the circuit works as a slave tr ansmitter with the address lsb set high or as a slave receiver with the lsb set low. in receive mode, the first data byte is written to the radd virtual register, which form s the register address. the radd register takes an 8-bit value that determines which of 256 possible regist er addresses is written to by the following byte. not all addresses are valid and many are reserved registers that must not be changed from their default values. multiple byte reads or writes will auto-in crement the value in radd, but care should be taken not to access the reserved registers accidentally. following a valid chip address, the 2-wire bus stop comma nd resets the radd register to 00. if the chip address is not recognized, the zl10210 will igno re all activity until a valid chip address is received. the 2-wire bus start command does not reset the radd register to 00. this allows a combined 2-wire bus message, to point to a particular read register with a writ e command, followed immediately with a read data command. if required, this could next be followed with a write command to continue from the latest address. radd would not be sent in this case. finally, a stop command should be sent to free the bus. when the 2-wire bus is addressed (after a recognized stop command) with the read bit se t, the first byte read out is the contents of register 00. 2.1.2 tuner the zl10210 has two gpp (general purpos e port) pins which are normally co nfigured to provide a secondary 2-wire bus, allowing the main serial bus to be connect ed through to the tuner only when it is necessary to communicate with the tuner. this reduces the electrical noise seen by the tuner and improves the performance. the allocation of the pins is: pin45=clk2 or gpp3; pin46=data2 or gpp2. pass-through mode is selected by setting register tuner_ctl (0 x56) [b0] = ?1?, otherwise, if this bit is ?0?, then there is no connection between the two serial buses. in this same register, bit [b2] must also be set to a ?1? to enable the pins for serial use rather than as ge neral purpose port pins. see also register gpp_ctl address 0x55 for details of using these pins as gpps. addr[7] addr[6] addr[5] addr[ 4] addr[3] addr[2] addr[1] not programmable sadd[4] sa dd[3] sadd[2] sadd[1] sadd[0] gnd gnd gnd vdd vdd vdd vdd
zl10210 data sheet 10 zarlink semiconductor inc. 2.1.3 examples of 2-wire bus messages: write operation - as a slave receiver: read operation - zl10210 as a slave transmitter: write/read operation with repeated start - zl10210 as a slave transmitter: 2.1.4 primary 2-wire bus timing figure 5 - primary 2-wire bus timing where: s = start sr = restart, i.e., start without stopping first p=stop key: s start condition w write (= 0) p stop condition r read (= 1) a acknowledge na not acknowledge italics zl10210 output radd register address s device w a radd a data a data a p address (n) (reg n) (reg n+1) s device r adata a data a data na p address (reg 0) (reg 1) (reg 2) sdevice w a radd a s device r adata a data na p address (n) address (reg n) (reg n+1) p s sr p low t t r t hd;sta hd;dat t t f high t t su;dat su;sta t data1 clk1 t buff t su;sto
zl10210 data sheet 11 zarlink semiconductor inc. 2.2 mpeg 2.2.1 data output header format figure 6 - dvb transport packet header byte parameter symbol value unit min. max. clk clock frequency (primary) f clk 0 400 1 1. if operating with an external 4 mhz clock, the serial clock frequency is reduced to 100 khz maximum. khz bus free time between a stop and start condition. t buff 200 ns hold time (repeated) start condition. t hd;sta 200 ns low period of clk clock. t low 1300 ns high period of clk clock. t high 600 ns set-up time for a repeated start condition. t su;sta 200 ns data hold time (when input). t hd;dat 100 ns data set-up time t su;dat 100 ns rise time of both clk and data signals. t r note 2 2. the rise time depends on the external bus pull up resistor. loading prevents full speed operation. ns fall time of both clk and data signals, (100pf to ground). t f 20 ns set-up time for a stop condition. t su;sto 200 ns table 3 - timing of 2-wire bus tei 01000111 1st byte 2nd byte transport packet header 4 bytes 184 transport packet bytes 188 byte packet output mdo [ 7 ] mdo [ 0 ]
zl10210 data sheet 12 zarlink semiconductor inc. after decoding the 188-byte mpeg packet, it is out put on the mdo pins in 188 consecutive clock cycles. additionally when the tei_en bit in the mclk_ctl regist er (0x77) is set high (default), the tei bit of any uncorrectable packet will automatically be set to ?1?. if tei_en bit is low then tei bit will no t be changed (but note that if this bit is already 1, for ex ample, due to a channel error which has not been corrected, it will remain high at output). 2.2.2 mpeg data output signals the mpegen bit in the config register must be set low to enable the mpeg data pins as outputs. the maximum movement in the packet synchronization byte position is limited to 1 output cloc k period. moclk will be a continuously running clock once symbol lock has been achi eved, and is derived from the symbol clock. moclk is shown in figure 7 with moclkinv = ?1?, th e default state, s ee register 0x50. all output data and signals (mdo[7:0], mostrt, moval & bkerr ) change on the negative edge of moclk (moclkinv = 1) to present stable data and si gnals on the positive edge of the clock. a complete packet is output on mdo[7:0] on 188 consecutiv e clocks and the mdo[7:0] pins will remain low during the inter-packet gaps. mostrt goes high for the first byte clock of a packet. moval goes high on the first byte of a packet and remains high until the last byte has been clocked out. bkerr goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the last byte has been clocked out. figure 7 - mpeg output data waveforms 2.2.3 mpeg output timing maximum delay conditions: vdd = 3.0 v, cvdd = 1.62 v, tamb = 85 o c, output load = 10 pf. minimum delay conditions: vdd = 3.6 v, cvdd = 1.98 v, tamb = -40 o c, output load = 10 pf. moclk frequency = 45.06 mhz. mdo7:0 moclkinv=1 moclk mostrt moval bkerr tp ti 1st byte packet n 188 byte packet n 1st byte packet n+1
zl10210 data sheet 13 zarlink semiconductor inc. 2.2.4 moclkinv = 1 figure 8 - mpeg timing - moclkinv = 1 2.2.5 moclkinv = 0 mdoswap = 0 the hold time is better when moclkinv = 1, th erefore this should be used if possible. figure 9 - mpeg timing - moclkinv = 0 parameter delay conditions units maximum minimum data output delay t d 3.0 1.0 ns setup time t su 7.0 10.0 hold time t h 7.0 10.0 parameter delay conditions units maximum minimum data output delay t d 3.0 1.0 ns setup time t su 18.0 20.0 hold time t h 1.0 0.2 t d t su moclk mdo mostrt moval bkerrb } t h bkerr t d t su moclk mdo mostrt moval bkerrb } t h bkerr
zl10210 data sheet 14 zarlink semiconductor inc. 3.0 electrical characteristics 3.1 recommended operating condition 3.2 absolute maximum ratings note 1: stresses exceeding these listed under 'absolute ratings' may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or ab ove these conditions is not implied. parameter symbol min. typ. max. units core power supply voltage cvdd 1.71 1.8 1.89 v periphery power supply voltage vdd 3.13 3.3 3.47 v input clock frequency (note ? ) ?. when not using a crystal, xti may be driven from an external source over the frequency range shown. fxt1 3.99 27.01 mhz crystal oscillator frequency fxt2 9.99 16.01 mhz clk1 clock frequency ? (with 10 mhz or above) ?. the maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 khz wi th a 4.0 mhz clock. fclk1 400 khz ambient operating temperature -40 85 c maximum operating conditions parameter symbol min. max unit power supply vdd -0.3 4.5 v cvdd -0.3 2.3 voltage on input pins (5 v rated) vi -0.3 5.5 v voltage on input pins (3.3 v rated) vi -0.3 6.5 v voltage on input pins (1.8 v rated, e.g., xti ) vi -0.3 cvdd + 0.3 v voltage on output pins (5 v rated) vo -0.3 5.5 v voltage on output pins (3.3 v rated) vo -0.3 vdd + 0.3 v voltage on output pins (1.8 v rated, e.g., xto) vo -0.3 cvdd + 0.3 v storage temperature tstg -55 150 c operating ambient temperature top -40 85 c junction temperature tj 125 c esd protection (human body model) 4 kv
zl10210 data sheet 15 zarlink semiconductor inc. 3.3 crystal specification parallel resonant fundamental frequency (preferred) 9.99 to 16.01 mhz. tolerance over operating temperature range 25 ppm. tolerance overall 50 ppm. nominal load capacitance 30 pf. equivalent series resistance <50 ? figure 10 - crystal oscillator circuit 3.3.1 selection of external components the capacitor values used must ensure correct operat ion of the pierce oscillator su ch that the total loop gain is greater than unity. correct selection of the two capacitors is ve ry important and the following method is recommended to obtain values for c1 and c2. 3.3.1.1 loop gain equation although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to ensure that oscillations will occur across all variations in temperature, process an d supply voltage, and that the circuit will exhibit good start-up characteristics. - equation 1 - equation 2 3.3.1.2 list of equation parameters a total loop gain (between 5 and 25) cin c1 + cpar cout c2 + cpar cpar parasitic capacitance associated with each oscillator pin (xti and xto). it consists of track capacitances, package capacitance and cell input capacitance. normally cpar 4pf. zo 9.143 k ? - output impedance of amplifie r at 1.8 v operation - typical a = c out .g m c in c out + c in r f .c in + 1 z in -1 1 z o + z in = 1 (2. .f.c out ) 2 .esr
zl10210 data sheet 16 zarlink semiconductor inc. 3.3.1.3 calculating crystal power dissipation to calculate the power dissipated in a crystal the following equation can be used: - equation 3 pc = power dissipated in crystal at resonant frequency (w) vpp = maximum peak to peak output swing of amplifier is 1.8 v for all cvdd zin = crystal network impedance (see equation 2) 3.3.1.4 capacitor values using the loop gain limits (5 < a < 25), the maximum and minimum values for c1 and c2 can be calculated with equation 4 below. - equation 4 note: equation 4 was derived from equation 1 and equation 2 using the premise that c1 = c2. within these limits, any value for c1 and c2 can now be selected. normally c1 and c2 are chosen such that the resulting crystal load capacitance c l (see equation 5) is close to t he crystal manufacturers recommended c l (standard values for c l are 15 pf, 20 pf and 30 pf). the crystal will then operate very near its specified frequency. - equation 5 c par12 = parasitic capacitance between the xti and xto pins. it consists of the ic package?s pin-to-pin capacitance (including any socket used) and the printed circuit board?s track-to-track capacitance. c par12 2pf. if some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer?s recommended c l may be acceptable. larger values of c l tend to reduce the influence of circuit variations and tolerances on frequency stability. smaller values of c l tend to reduce startup time and crystal power dissipation. care must however be taken that c l does not fall outside the crystal pulling range or the circuit may fail to start up altogether. it is al so possible to quote c l to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load conditions, at the desired frequency. finally the power dissipation in the crystal must be checked. if pc is too high c1 and c2 must be reduced. if this is not feasible c2 alone may be reduced. unbalancing c1 and c2 will, however, require checking if the loop gain condition is still satisfied. th is must be done using equation 1. gm 8.736ma/v - transconductance of amplif ier at 1.8 v operation -typical rf 2.3m ? - internal feedback resistor esr maximum equivalent series resistance of crystal - given by crystal manufacturer ( ? ) f fundamental frequency of crystal (hz) p c = 8.z in v pp 2 c in = c out = g m a 2 r f 1 z o 1 (2. .f) 2 .esr when: c 1 = c 2 = c out - c par -- . c l = c out . c in c out + c in + c par12 note: 2 > c 2 c 1 > 0.5
zl10210 data sheet 17 zarlink semiconductor inc. 3.3.1.5 oscillator/c lock application notes ? on the printed circuit board, the tracks to the crysta l and capacitors must be made as short as possible. other signal tracks must not be allowed to cross through this area. the component tracks should preferably be ringed by a ground track connected to the chip ground (0 v) on adjacent pins either side of the crystal pins. it is also advisable to provide a gr ound plane for the circuit to reduce noise. ? external clock signals, applied to xti and/or xto, must not exceed the cell supply limits (i.e., 0 v and cvdd) and current into or out of xti and/or xto must be limited to less than 10ma to avoid damaging the cell?s amplitude clamping circuit. ? an external, dc coupled, single ended squar e wave clock signal may be applied to xti if oscmode = 0. to limit the current taken from the signal source a re sistor should be placed between the clock source and xti . the recommended value for this series resistor is 470 ? for a clock signal switching between 0v and cvdd (1v8) . the current the clock source needs to source/sink is then < 1.9 ma. the xto pin must be left unconnected in this configuration. ? ac coupling of a single ended external clock to xti , with oscmode = 0, is not recommended. the duty cycle of the oscout signal cannot be guaranteed in such a configuration. ? ac coupling of a single ended external clock to xti , with oscmode = 1, is possible. it is recommended that the circuit shown in figure 11 be used to correctly bias the oscillator inputs: the common-mode voltage vcm for xti and xto, (set by the 15 k ? and 22 k ? resistors) must be 800 mv < vcm < cvdd and the amplitude vpp of the clock signal must be >400 mv. figure 11 - external clocking via ac coupling ? external, differential clock signals may be applied to xti and xto if oscmode = 1. the common-mode voltage vcm for the differential clock signals must be 800 mv < vcm < cvdd, and the peak-to-peak signal amplitude vpp must be >400 mv. it is recommended that differential clock signals have vcm = 1.0 v. for vpp > 400 mv a resistor of > 390 ? in series with xti or xto may be required to limit the current taken from or supplied to the clock sources. external clock 10nf xti 100k 10nf 22k 36k xto vdd oscmode
zl10210 data sheet 18 zarlink semiconductor inc. 3.4 electrical characteristics conditions (unless specified otherwis e): tamb = 25c cvdd = 1.8 v vdd = 3.3 v dc electrical ch aracteristics parameter conditions/pin symbol min. typ. max. unit core voltage cvdd 1.71 1.8 1.89 v peripheral voltage vdd 3.13 3.3 3.47 v core current default settings cidd 120 ma peripheral current idd 2.2 ma total power ptot1 223 mw to ta l p o w e r (stand-by) adcs powered down. mpeg outputs tri-stated ptot2 2.55 mw total power (sleep) pin 20 = logic ?1? & adcs powered down ptot3 0.10 mw output low level 2, 6 or 12 ma per output (see section 1.3, pin description) vol 0.4 v output high level 2, 6 or 12 ma per output voh 2.4 v output leakage tri-state when off or open-drain when high 1 a output capacitance all outputs except xto, clk1 & open-drain types. excludes packaging contribution (~0.35pf) 2.7 pf open-drain outputs. excludes packaging contribution (~0.35pf) 3.3 pf input low level vil 0.8 v input high level vih 2.0 v input leakage vin = 0 or vdd 1 a input capacitance excludes packaging contribution (~0.35pf) 1.5 pf
zl10210 data sheet 19 zarlink semiconductor inc. ac electrical characteristics parameter conditions/pin min. typ. max. unit adc full-scale input single range (single-ended or differential) differential source is recommended 1.6 vpp adc analog input resistance per input pin 25 k ? adc input common mode voltage level 0.9 ? v rf adc full-scale input single range (single-ended) 3.3 vpp rf adc analog input resistance 25 k ? rf adc input common mode voltage 1.65 ? v system clock frequency 30.00 100 mhz input clock frequency (note ?? ) see section 3.3.1.5 for details. 3.99 27.01 mhz crystal oscillator frequency see se ction 3.3 for details 9.99 16.01 mhz clk1 clock frequency ?? (with 10 mhz xtal or above) 400 khz mpeg clock input frequency on pin #63 note ??? 65 ??? mhz ?. actually cvdd/2 ?. actually vdd/2 ??. when not using a crystal, xti may be driven from an external source over the frequency range shown. ??. the maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 khz w ith a 4.0 mhz clock. ???. must be calculated from the data input rate. ???. must be lower than the system clock.

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